Memory systems, such as those based on Double Data Rate (DDR) Synchronous Dynamic Random-Access Memory (SDRAM), define and use a set of data strobe (DQS) signals to strobe (e.g., sample) data during a memory write operation, and a set of (corresponding) input/output data (DQ) signals for writing data bits to, and reading data bits from, a memory module (e.g., DRAM module).
Generally, a particular DQS signal is generated by a memory controller during a write operation, where each transition of a DQS signal indicates a sample point for a particular DQ signal and the DQS signal has a setup/hold requirement when memory (e.g., DRAM module) uses it to strobe (e.g., sample) the particular DQ signal. Additionally, memory systems may further use a set of data mask (DM) signals to indicate which DQ signals should be interpreted as valid data or non-valid data during a sampling period, which is indicated by corresponding DQS signals. Accordingly, the timing of DQ signals and DM signals, relative to DQS signals, can be important for proper operation of a memory system.
To improve memory access signals between a memory module (e.g., DRAM modules) and a memory controller, a memory system performs a training (or calibration) process that delays a DQ signal relative to its corresponding DQS signal such that the DQS signal is centered with of a data eye of the DQ signal and the data eye of the DQ signal arriving at a receiver latch (of the memory module) centered on the transition of the DQS signal. The range timing from the beginning to the end of valid data is referred to as a valid data eye, which is defined by two edges. Data between the two edges is considered valid and can be correctly latched by the memory module, while data outside of the two edges are considered invalid. Accordingly, the DQS signal should fall between the edges of the data eye to obtain correct data, the DQS signal should fall between the edges of the data eye for the memory to obtain correct data during a memory write operation. The data eye tends to become narrower as memory speeds increase and various conditions relating to a memory system (e.g., printed circuit board (PCB) delays) can cause the data eye to drift.
Though certain memory systems, such as Low Power Double Data Rate 4 (LPDDR4) memory systems, have a WDQ training process for delaying a DQ signal relative to its corresponding DQS signal, other memory systems, such as Double Data Rate 3 (DDR3), Double Data Rate 4 (DDR4), Low Power Double Data Rate 3 (LPDDR3) and other memory systems, lack a training process for delaying a DQ signal relative to its corresponding DQS signal. Additionally, as memory systems, such as those using DRAM, operate at higher and higher data rates (e.g., 3.2 Gb for DDR4), it becomes difficult to ensure timing of DQ. DM, and DQS signals, thereby making training of such signals essential for proper memory system operation.